Data processors that utilize hardware multipliers implement multipliers as either an integer hardware multiplier or a floating-point hardware multiplier. The output of an integer hardware multiply operation is non-fractional whereas the output of a floating-point hardware multiply operation is expressed using an exponential portion, a sign portion and a mantissa portion. Illustrated in FIG. 1 is a floating-point multiply operation which generally comprises the multiplication of two n-bit sized normalized mantissas, where n is an integer. The multiplication of the two n-bit sized operands produces a (2n) bit sized product output. The data output format of a floating-point hardware multiplier generally adheres to standards established within the IEEE Standard for Binary Floating-Point Arithmetic (ANSI-IEEE Std 754-1985). One aspect of the standard involves the rounding precision to which the output is represented. Various pieces of information are required to implement the rounding procedure; one such piece of information is a "Sticky-Bit", where a Sticky-Bit is the logical OR of a predetermined portion, typically (n-2) bits of the lower order output bits. Known methods for implementing Sticky-Bit detection differ in one way by having differing multiplier circuit area requirements and differing amounts of time required to calculate a Sticky-Bit condition. Referring to FIG. 1, a common method of calculating the Sticky-Bit is illustrated in diagrammatic form. All of the (2n) product bits are calculated before preforming the logical OR of the least significant (n-2) product bits. This method requires additional multiplier hardware since circuitry is required to calculate product bits which are subsequently truncated. Also, additional time for the multiply operation is required to calculate all of the product bits before beginning the Sticky-Bit operation. Therefore, overall system performance of a data processor system having a multiplier is reduced.